description designed for pulse width modulated (pwm) control of low voltage stepper motors, and single and dual dc motors, the a3906 is capable of output currents up to 1 a per channel and operating voltages from 2.5 to 9 v. the a3906 has an internal fixed off-time pwm timer that sets a peak current based on the selection of a current sense resistor. an overcurrent output flag is provided that notifies the user when the current in the motor winding reaches the peak current determined by the sense resistor. the fault output does not affect driver operation. the a3906 is provided in a 20-contact, 4 mm 4 mm, 0.75 mm nominal overall height qfn, with exposed pad for enhanced thermal dissipation. it is lead (pb) free, with 100% matte tin leadframe plating. applications include the following: ? digital still cameras (dsc) ? cell phone cameras ? usb powered devices ? battery powered devices features and benefits ? 2.5 to 9 v operation ? internal pwm current limit control ? synchronous rectification for reduced power dissipation ? peak current output flag ? undervoltage lockout ? low r ds(on) outputs ? small package ? brake mode for dc motors ? sleep function ? crossover-current protection ? thermal shutdown low voltage stepper and single/dual dc motor driver package: 20-contact qfn (suffix es) typical applications a3906 approximate size 3906-ds, rev. 4 out1a out1b vbb vcp cp4 cp3 sense1 out2a out2b sense2 10 f 10 v +5 v m m 0.1 f 0.1 f cp2 cp1 0.1 f a3906 in1 in2 in3 in4 fl1 fl2 gnd sleep dual dc motor application out1a out1b vbb vcp cp4 cp3 sense1 out2a out2b sense2 10 f 10 v +5 v m 0.1 f 0.1 f cp2 cp1 0.1 f a3906 sleep in1 in2 in3 in4 fl1 fl2 gnd stepper motor application
low voltage stepper and single/dual dc motor driver a3906 2 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com absolute maximum ratings characteristic symbol notes rating units load supply voltage v bb 9.6 v logic input voltage range v in ?0.3 to 7 v sense voltage v sensex continuous 0.5 v pulsed, t w < 1 s1v output current i out may be limited by duty cycle, ambient temperature, and heat sinking. under any set of conditions, do not exceed the specified current rating or a junction temperature of 150c. continuous 1 a peak, dc < 30% 1.5 a output current in paralleled operation i out(par) continuous 2 a peak, dc < 30% 2.5 a operating temperature range t a range s ?20 to 85 c junction temperature t j(max) 150 c storage temperature range t stg ?40 to 150 c selection guide part number packing package a3906sestr-t 1500 pieces per 7-in. reel 20-pin qfn with exposed thermal pad thermal characteristics may require derating at maximum conditions, see application information characteristic symbol test conditions* value units package thermal resistance r ja 4-layer pcb based on jedec standard 37 oc/w *additional thermal information available on the allegro website. terminal list table number name function 1 cp2 charge pump capacitor terminal 2 2 gnd ground 3 sleep sleep logic input, active low 4 in1 control input 5 in2 control input 6 in3 control input 7 in4 control input 8 fl1 current limit flag, bridge 1 9 fl2 current limit flag bridge 2 10 out2a dmos full-bridge 2, output a 11 sense2 current sense resistor terminal, bridge 2 12 out2b dmos full-bridge 2, output b 13 vbb supply voltage 14 out1b dmos full-bridge 1, output b 15 sense1 current sense resistor terminal, bridge 1 16 out1a dmos full-bridge 1, output a 17 vcp reservoir capacitor terminal 18 cp3 charge pump capacitor terminal 3 19 cp1 charge pump capacitor terminal 1 20 cp4 charge pump capacitor terminal 4 ? pad exposed pad for enhanced thermal performance pad 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 cp4 cp1 cp3 vcp out1a in3 in4 fl1 fl2 out2a sense1 out1b vbb out2b sense2 cp2 gnd sleep in1 in2 pin-out diagram
low voltage stepper and single/dual dc motor driver a3906 3 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com out1a out1b out2a out2b vbb gnd in1 in2 in3 vbb vbb 10 f 10 v in4 vcp cp1 cp2 charge pump sense2 rs2 rs1 sense1 control logic sense1 sense2 fl1 fl2 sleep vcp vcp sense2 sense1 regulator +5 v 0.1 f 0.1 f pwm latch and blanking comparator bridge 1 pwm latch and blanking comparator bridge 2 +5 v cp3 cp4 0.1 f functional block diagram
low voltage stepper and single/dual dc motor driver a3906 4 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com electrical characteristics 1,2 valid at t a = 25c and v bb = 2.5 to 9 v, unless otherwise noted characteristics symbol test conditions min. typ. max. units operating voltage range v bb 2.5 ? 9 v vbb supply current i bb i out = 0 ma, pwm = 50 khz, duty cycle = 50% ? 5 ? ma i out = 0 ma, outputs disabled, v bb = 9.6 v ? 3 ? ma sleep mode, v in < 0.4 v ? 150 500 na output resistance r ds(on) source driver, i out = 400 ma , v bb = 3 v, t j = 25c ? 0.52 0.60 source driver, i out = 400 ma , v bb = 3 v, t j = 85c ? 0.78 ? sink driver, i out = 400 ma, v bb = 3 v, t j = 25c ? 0.62 0.74 sink driver, i out = 400 ma, v bb = 3 v, t j = 85c ? 0.93 ? current trip sense voltage v sense flx falling edge 160 200 240 mv clamp diode voltage v f i = 400 ma ? ? 1 v output leakage current i dss outputs, v out = 9 v ?20 ? 20 a control logic logic input voltage v in(1) 2.0 ? 5.5 v v in(0) ? ? 0.8 v logic input current i in(1) v in = 5.5 v ? <100 500 na i in(0) v in = 0.8 v ? low voltage stepper and single/dual dc motor driver a3906 5 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com i load flx i trip t flx t flx fault asserted fault asserted fault asserted note: timer resets after each reset of the pwm latch. fault timing diagram dc motor operation in1 in2 in3 in4 out1a out1b out2a out2b function 0 0 0 0 off off off off disabled 1 0 1 0 high low high low forward 0 1 0 1 low high low high reverse 1 1 1 1 low low low low brake stepper motor operation in1 in2 in3 in4 out1a out1b out2a out2b function 0 0 0 0 off off off off disabled disabled 1 0 1 0 high low high low full step 1 ? step 1 0 0 1 0 off off high low ? ? step 2 0 1 1 0 low high high low full step 2 ? step 3 0 1 0 0 low high off off ? ? step 4 0 1 0 1 low high low high full step 3 ? step 5 0 0 0 1 off off low high ? ? step 6 1 0 0 1 high low low high full step 4 ? step 7 1 0 0 0 high low off off ? ? step 8 control logic
low voltage stepper and single/dual dc motor driver a3906 6 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com device operation the a3906 is a dual full-bridge low volt- age motor driver capable of operating one stepper motor, two dc motors, or one high current dc motor. mosfet output stages substantially reduce the voltage drop and the power dissipation of the outputs of the a3906, compared to typical drivers with bipolar transistors. output current can be regulated by pulse width modulating (pwm) the inputs. in addition supporting external pwm of the driver, the a3906 limits the peak current by internally pwming the source driver when the current in the winding exceeds the peak current, which is determined by a sense resistor. a fault output notifies the user that peak current was reached. if internal current limiting is not needed, the sense pin should be shorted to ground. internal circuit protection includes thermal shutdown with hyster- esis, undervoltage lockout, internal clamp diodes, and crossover current protection. the a3906 is designed for portable applications, providing a power-off low current sleep mode and an operating voltage of 2.5 to 9 v. external pwm output current regulation can be achieved by pulse width modulating the inputs. slow decay mode is selected by holding one input high while pwming the other input. hold- ing one input low and pwming the other input results in fast decay. refer to the applications information section for further information. blanking this function blanks the output of the current sense comparator when the outputs are switched. the comparator output is blanked to prevent false overcurrent detections due to reverse recovery currents of the clamp diodes or to switching transients related to the capacitance of the load. the blank time, t blank , is approximately 3 s. sleep mode an active-low control input used to minimize power consumption when the a3906 is not in use. this dis- ables much of the internal circuitry including the output drivers, internal regulator, and charge pump. a logic high allows normal operation. when coming out of sleep mode, wait 1.5 ms before issuing a command, to allow the internal regulator and charge pump to stabilize. enable when all logic inputs are pulled to logic low, the outputs of the bridges are disabled. the charge pump and internal cir- cuitry continue to run when the outputs are disabled. charge pump (cp1, cp2, cp3, and cp4) when supply volt- ages are lower than 3.5 v, the two-stage charge pump triples the input voltage to a maximum of 7 v above the supply. the charge pump is used to create a supply voltage greater than v bb , to drive the source-side dmos gates. for pumping purposes, a 0.1 f ceramic capacitor should be connected between cp1 and cp2, and between cp3 and cp4. a 0.1 uf ceramic capacitor is required between vcp and vbb, to act as a reservoir to operate the high- side dmos devices. thermal shutdown the a3906 will disable the outputs if the junction temperature reaches 165c. when the junction tempera- ture drops 15c, the outputs will be enabled. brake mode when driving dc motors, the a3906 goes into brake mode (turns on both sink drivers) when both of its inputs are high (in1 and in2, or in3 and in4). there is no protection during braking, so care must be taken to ensure that the peak current during braking does not exceed the absolute maximum current. internal pwm current control each full-bridge is controlled by a fixed off-time pwm current control circuit that limits the load current to a desired value, i trip . initially, a diagonal pair of source and sink dmos outputs are enabled and current flows through the motor winding and the current sense resistor, rsx. when the voltage across rsx equals the internal reference volt- age, the current sense comparator resets the pwm latch, which turns off the source driver. the maximum value of current limiting, i trip (max) , is set by the selection of the sense resistor, rsx, and is approximated by a transconductance function: i trip (max) = 0.2 / r s . it is critical to ensure the maximum rating on sensex pins (0.5 v) is not exceeded. synchronous rectification when a pwm off-cycle is trig- gered by an internal fixed off-time cycle, load current recirculates in slow decay sr mode. during slow decay, current recirculates through the sink-side fet and the sink-side body diode. the sr feature enables the sink-side fet, effectively shorting out the body diode. the sink driver is not enabled until the source driver is turned off and the crossover delay has expired. this feature helps lower the voltage drop during current recirculation, lower- ing power dissipation in the bridge. overcurrent output flag when the peak current (set by the external resistor) is reached, the fault pin, flx, is pulled low. when a reset of the pwm latch occurs, the fault timer begins. at each pwm latch reset, the timer is reset to zero. after approxi- mately 300 s, if no peak current event was triggered, the timer expires and the fault is released. this ensures that during pwm current limiting, the fault pin remains in a fault state. functional description
low voltage stepper and single/dual dc motor driver a3906 7 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com applications information v in(1) v in(1) v in(1) v in(1) in1 gnd in2 gnd in3 gnd in4 gnd + v bb / r motor ? v bb / r motor i out1 , i out2 i out3 , i out4 0a + v bb / r motor ? v bb / r motor 0a full step sleep half step reverse/ fast decay reverse/ slow decay forward/ fast decay forward/ slow decay gnd gnd +i reg 0 a -i reg in1, in3 in2, in4 i outx v in(1) v in(1) external pwm if external pwm is used, the internal current control can either be disabled by shorting the sensex pin to ground, or it can be used to limit the peak current to a value under the stall current to prevent motor heating. external pwm in1 control is shown in the upper figure. stepper motor control the a3906 also can be used to control a bipolar stepper motor. the control logic for stepper motor control is shown in the lower figure. the driver is capable of operating in full- and half-step modes. pwm current control in fast and slow decay modes stepper motor control in full- and half-step modes
low voltage stepper and single/dual dc motor driver a3906 8 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com parallel operation the a3906 can be paralleled for applica- tions that require higher output currents. in paralleled mode the driver can source 2 a continuous. the a3906 has two completely independent bridges with separate overcurrent latches. this allows the device to supply two separate loads, and as a result, when paralleled it is imperative that the internal current control is disabled by shorting the sense pins to ground. because the overcurrent trip threshold is internally fixed at 0.2 v, the trace resistance must be kept small so the internal current latch is not triggered prematurely. with acceptable margin, the voltage drop across the trace resistance should be under 0.1 v. at a peak current of 2.5 a, the trace resistance should be kept below 40 m to prevent false tripping of the overcurrent latch. each bridge has some variation in propagation delay. during this time it is possible that one bridge will have to support the full load current for a very short period of time. propagation delays are characterized and guard banded to protect the driver from damage during these events. layout the printed circuit board should use a heavy ground- plane. for optimum electrical and thermal performance, the a3906 must be soldered directly onto the board. on the under- side of the a3906 package is an exposed pad, which provides a path for enhanced thermal dissipation. the thermal pad should be soldered directly to an exposed surface on the pcb. thermal vias are used to transfer heat to other layers of the pcb. grounding in order to minimize the effects of ground bounce and offset issues, it is important to have a low impedance single- point ground, known as a star ground , located very close to the device. by making the connection between the exposed thermal pad and the ground plane directly under the a3906, that area dc motor operation (parallel bridge) in1/in3 in2/in4 out1a/2a out1b/2b function 0 0 off off disabled 1 0 h l for 0 1 l h rev 1 1 l l brake out1a out1b out2a out2b vbb gnd in1 in2 in3 10 f 10 v in4 vcp cp1 cp2 sense2 sense1 fl1 fl2 0.1 f 0.1 f a3906 cp1 cp2 0.1 f sleep
low voltage stepper and single/dual dc motor driver a3906 9 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com out1a u1 c1 gnd gnd out1b vbb out2b out2a c2 c3 +5v r1 r2 r4 r3 cp4 cp1 cp3 vcp out1a in3 in4 fl1 fl2 out2a sense1 out1b vbb out2b sense2 cp2 gnd sleep in1 in2 pad a3906 c2 c3 c1 r1 r3 r4 r2 out1a out1b out2b out2a +5v vbb pcb thermal vias trace (2 oz.) signal (1 oz.) ground (1 oz.) thermal (2 oz.) solder a3906 pcb layout becomes an ideal location for a star ground point. a low imped- ance ground will prevent ground bounce during high current operation and ensure that the supply voltage remains stable at the input terminal. the recommended pcb layout shown in the diagram below, illustrates how to create a star ground under the device, to serve both as low impedance ground point and thermal path. the two input capacitors should be placed in parallel, and as close to the device supply pins as possible. the ceramic capaci- tor should be closer to the pins than the bulk capacitor. this is necessary because the ceramic capacitor will be responsible for delivering the high frequency current components. sense pins the sense resistors, rs x , should have a very low impedance path to ground, because they must carry a large cur- rent while supporting very accurate voltage measurements by the current sense comparators. long ground traces will cause additional voltage drops, adversely affecting the ability of the comparators to accurately measure the current in the windings. as shown in the layout below, the sense x pins have very short traces to the rs x resistors and very thick, low impedance traces directly to the star ground underneath the device. if possible, there should be no other components on the sense circuits. note: when selecting a value for the sense resistors, be sure not to exceed the maximum voltage on the sense x pins of 500 mv.
low voltage stepper and single/dual dc motor driver a3906 10 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com es package, 20-contact qfn with exposed thermal pad copyright ?2008-2013, allegro microsystems, llc allegro microsystems, llc reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions a s may be required to permit improvements in the per for mance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro?s products are not to be used in life support devices or systems, if a failure of an allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. the in for ma tion in clud ed herein is believed to be ac cu rate and reliable. how ev er, allegro microsystems, llc assumes n o re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. for the latest version of this document, visit our website: www.allegromicro.com 0.95 c seating plane c 0.08 21x 20 20 2 1 1 2 20 2 1 a a terminal #1 mark area coplanarity includes exposed thermal pad and terminals b exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) for reference only (reference jedec mo-220wggd) dimensions in millimeters exact case and lead configuration at supplier discretion within limits shown c d d c reference land pattern layout (reference ipc7351 qfn50p400x400x80-21bm) all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances; when mounting on a multilayer pcb, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference eia/jedec standard jesd51-5) 4.10 0.30 0.50 4.10 0.50 0.75 0.05 2.45 2.45 0.25 +0.05 ?0.07 0.40 +0.15 ?0.10 4.00 0.15 4.00 0.15 2.45 2.45 b pcb layout reference view
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